Computers are often employed for safety-critical functions in state-of-the-art transportation systems. Computers may be coupled with sensor systems, configured to sense operations of the transportation system, and to react to possible dangerous situations with a speed and dependability that is unmatched by human capabilities. For example, in automobiles a computer based sensor may be used to regulate the operation of airbags, braking systems, etc.
Safety-critical computer systems often rely upon data stored in a memory (e.g., flash, SRAM, DRAM, etc.) for proper operation. Error correction code (ECC) may be implemented to improve the reliability of memories used to perform safety-critical functions through detecting and correcting memory cell errors. Some error correction codes may be used to detect and correct single-bit errors (e.g., one invalid bit in a particular memory word may be able to be corrected and determined by SECDED). Other, more sophisticated error correction codes, allow the detection and/or correction of double-bit errors (e.g., two invalid bits in a particular memory word may be able to be corrected and determined by DECTED) or even multiple bit errors (e.g., triple bit errors).
FIG. 1 illustrates a block diagram 100 showing an exemplary memory block 102 configured to implement an error correcting mechanism with the use of ECC. As illustrates in FIG. 1, the memory block 102 may comprise a memory array 104, having multiple bitlines activated by a sense amplifier 106 and multiple wordlines activated by a row decoder 108. Respective MOS transistor devices (not shown) configured to store charges corresponding to data bits, may have a first terminal coupled to a bitline, a second terminal coupled to a shared or single source line, and a gate coupled to a wordline.
In order to perform error detection, the memory array 104 is configured to store data fields containing data alongside ECC information bits containing one or more check bits and/or parity bits. Therefore, in general, the memory array 104 includes a plurality of bitlines used in the storage of data bits and a plurality of bitlines used in the storage of ECC information.
When reading data, the data memory addresses, wherein information bits are to be written to, are transmitted together with ECC memory addresses. The data and ECC memory addresses are checked locally by address decoder 116 and address ECC check 114, respectively, before decoding the requested word and bit lines. The data bits and ECC information bits are then read from an address of the memory array 104 by selective activation of a wordline (with row decoder 108) and a bitline (with sense amplifier 106). In particular, during a read operation a wordline may be set to a high data state, thereby activating the gate of a MOS transistor device and causing data stored in the transistor to be driven to a bitline. ECC information bits, read from the memory array, may be used to detect and correct an error in associated data bits read from the memory array.
Similarly, when writing data, data bits and ECC information bits are written into the memory module by selective activation of a wordline (with row decoder 108) and one or more bitlines (with sense amplifier 106). For example, a voltage greater than the threshold voltage of a MOS transistor device may be applied to a wordline, thereby coupling the transistor to the bitline. A bitline is then raised, causing electrons or holes to be injected, to the floating gate. ECC information bits may be calculated, for data bits being written to the memory array, during the write process and written to memory locations associated with the data bits.